Matching Techniques & Blockers

1. ASM Barrier for Constant Load Scheduling SOLVED

Problem: agbcc loads literal pool constants after computing ALU operations on arguments. The original code loads constants before the ALU operations (filling pipeline stall slots).

ldr r1, =TABLE    ; load first
lsls r0, r0, #2   ; then compute
adds r0, r0, r1

lsls r0, r0, #2   ; compute first
ldr r1, =TABLE    ; then load
adds r0, r0, r1

Solution: Use an inline asm barrier to force the constant into a register at a specific point in the code:

u32 addr = 0x08189B4C;
u32 *table;
asm("" : "=r"(table) : "0"(addr));
// compiler now loads addr via ldr BEFORE any subsequent code

Matched: FinalizeLevelLayerSetup, LoadAndDecompressStream, TransitionToWorldMap, FadeOutController, SetupGfxCallbacks, all m4a stream commands, and ~20 more.

2. Shift-Pair Interleaving SOLVED

Problem: When zero-extending a parameter to u16 (lsls r0, #16; lsrs r0, #13), the original interleaves constant loads between the two shifts. agbcc keeps the shifts together.

lsls r0, r0, #16   ; start truncation
ldr r2, =BASE      ; interleaved load
ldr r1, =TABLE     ; interleaved load
lsrs r0, r0, #13   ; finish truncation

u32 shifted = idx << 16;
asm("" : "+r"(shifted)); // force materialization
asm("" : "=r"(base) : "0"(a0));
asm("" : "=r"(table) : "0"(a1));
shifted >>= 13; // now after the loads

Matched: GetEntityLookupData, InitSceneState, m4aSongNumStop, m4aMPlayCommand.

3. Integer Arithmetic for adds Operand Order SOLVED

Problem: table + offset compiles to adds rTABLE, rTABLE, rOFF (result in table's register), but the original has adds rOFF, rOFF, rTABLE (result in offset's register).

Solution: Use integer arithmetic instead of pointer arithmetic:

// Instead of: entry = table + offset;
// Write:
offset += (u32)table;
entry = (u8 *)offset;
// Result stays in offset's register

Matched: GetEntityLookupData, InitSceneState, m4aSongNumStop, m4aMPlayCommand.

4. Forced Dead Copy via register asm SOLVED

Problem: GCC 2.95 sometimes generates a copy instruction (adds r1, r0, #0) before modifying a value. Modern optimization would eliminate this dead copy. We need it for matching.

s32 result = (s32)a * (s32)b;
register s32 shifted asm("r1");
shifted = result;                // forces: adds r1, r0, #0
asm("" : "+r"(shifted));         // prevent optimization
if (result < 0) shifted += 0xFF; // modifies r1, checks r0

Matched: FixedMul8 (8.8 fixed-point multiply).

5. Memory-Before-Constant Scheduling SOLVED

Problem: When loading both a memory value and a constant, the compiler may schedule the constant load first. The original loads from memory first.

u32 val = sceneCtrl[0];       // memory load
asm("" : "+r"(val));          // force it to materialize NOW
u32 addr = 0x03005498;
u8 *fadeCounter;
asm("" : "=r"(fadeCounter) : "0"(addr)); // constant load AFTER

Matched: FadeOutController.

6. Return Type for Pop Register Selection SOLVED

Problem: Non-leaf functions end with pop {rN}; bx rN. Most use r0, but some use r1 (to preserve the return value in r0). agbcc always uses r0 for void functions.

Solution: Declare the function and its callee as returning u32. The compiler then preserves r0 for the return value and pops to r1.

u32 MidiProcessEvent(void);     // declare as returning u32
u32 MPlayMain_SetAndProcess(u32 val) {
    // ...
    return MidiProcessEvent();  // compiler uses pop {r1}; bx r1
}

Matched: MPlayMain_SetAndProcess.

7. -fprologue-bugfix Compiler Flag SOLVED

Problem: agbcc generates push {lr}; ... pop {r0}; bx r0 for leaf functions that don't need to save lr. The original uses direct bx lr.

Solution: Add -fprologue-bugfix to CC1FLAGS. This makes the compiler emit bx lr for true leaf functions (no calls, no callee-saved registers needed).

Matched: All leaf functions without callee-saved registers (ReadUnalignedU16, etc.).

8. Register Pinning via asm Calls SOLVED

Problem: agbcc's register allocator chooses different registers than the original for struct member access and multi-argument function calls. This causes widespread mismatches.

Solution: Use asm("") barriers to force the compiler to materialize values in specific registers at specific points. This pins the register allocation without changing the generated instructions:

register u32 val asm("r4") = someExpr;
asm("" : "+r"(val));  // force r4 to hold val here
// subsequent code uses r4 as the original did

Matched: Many m4a functions including SoundInfoInit, ply_voice, ply_bend, ply_bendr, ply_lfos, ply_lfodl, ply_mod, and numerous gfx stream commands.

9. -ftst Compiler Flag SOLVED

Problem: The original ROM uses tst Rn, Rm (test without storing result) for bitflag checks. agbcc generates ands Rd, Rn + cmp Rd, #0 instead.

Solution: A custom -ftst flag was added to the Dream-Atelier agbcc fork. It adds a *andsi3_tst combiner pattern in thumb.md that merges and + cmp #0 into tst. Enabled per-compilation-unit for m4a_1.c.

Matched: VoiceLookupAndApply and other m4a functions that check bit flags.

10. Integer Arithmetic for adds Operand Order SOLVED

Problem: base + offset compiles to adds rOFF, rOFF, rBASE (result in offset's register), but the original has adds rOFF, rBASE, rOFF or vice versa.

// Instead of: entry = (u8 *)(tbl + off);
// Write:
off += (u32)tbl;
entry = (u8 *)off;
// Controls which register gets the adds result

Matched: StreamCmd_SetBGScroll, ProcessHBlankWait.

11. Early Return for Branch Direction SOLVED

Problem: if (x < 0) { cleanup; return 0; } return 1; generates bge .Lstill_waiting (skip cleanup), but the original has blt .Lcleanup (jump to cleanup).

Solution: Use early return 1; before the cleanup code so the "still waiting" path is the fall-through, forcing the compiler to use blt for the forward branch to cleanup.

Matched: ProcessHBlankWait.

12. Variable Reuse for Register Reuse SOLVED

Problem: Sequential constants go to different registers. The original reuses r0 for multiple constants: movs r0, #0; strh; movs r0, #0xE8; ...

u16 val = 0;
buf[4] = val;     // movs r0, #0; strh r0, [r1, #8]
val = 0xE80;
buf[8] = val;     // movs r0, #0xE8; lsls r0, #4; strh r0, [r1, #16]
// Same variable → same register

Matched: InitLevelStateDefaults.